/*
 * Copyright     :  Copyright (C) 2021, Huawei Technologies Co. Ltd.
 * File name     :  hipciec50_ap_engine_reg_reg_offset.h
 * Project line  :  
 * Department    :  CAD Development Department
 * Author        :  kuangxiaobo/262329
 * Version       :  1.0
 * Date          :  
 * Description   :  PCIE Controller 5.0  Version 200
 * Others        :  Generated automatically by nManager V5.1 
 * History       :  kuangxiaobo/262329 2021/10/23 17:25:01 Create file
 */

#ifndef __HIPCIEC50_AP_ENGINE_REG_REG_OFFSET_H__
#define __HIPCIEC50_AP_ENGINE_REG_REG_OFFSET_H__

/* HIPCIEC50_AP_ENGINE_REG Base address of Module's Register */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE                       (0xB000)

/******************************************************************************/
/*                      HiPCIECTRL50V200 HIPCIEC50_AP_ENGINE_REG Registers' Definitions                            */
/******************************************************************************/

#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_INT_SEVERITY_REG                    (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x10)  /* interrupt severity register */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_DMA_SMMU_BYPASS_CFG_REG             (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x20)  
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_0_H_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x24)  /* high 16bit of DMA DAW 0 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_0_L_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x28)  /* low 32bit of DMA DAW 0 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_1_H_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x2C)  /* high 16bit of DMA DAW 1 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_1_L_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x30)  /* low 32bit of DMA DAW 1 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_2_H_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x34)  /* high 16bit of DMA DAW 2 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_2_L_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x38)  /* low 32bit of DMA DAW 2 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_3_H_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x3C)  /* high 16bit of DMA DAW 3 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_3_L_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x40)  /* low 32bit of DMA DAW 3 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_4_H_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x44)  /* high 16bit of DMA DAW 4 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_4_L_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x48)  /* low 32bit of DMA DAW 4 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_5_H_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x4C)  /* high 16bit of DMA DAW 5 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_5_L_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x50)  /* low 32bit of DMA DAW 5 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_6_H_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x54)  /* high 16bit of DMA DAW 6 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_6_L_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x58)  /* low 32bit of DMA DAW 6 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_LL_REG          (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x5C)  /* the MCTP cache/snp configuration DAW 0 low boundary low 32bit address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_LH_REG          (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x60)  /* the MCTP cache/snp configuration DAW 0 low boundary high 32bit address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_HL_REG          (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x64)  /* the MCTP cache/snp configuration DAW 0 high boundary low 32bit address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_HH_REG          (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x68)  /* the MCTP cache/snp configuration DAW 0 high boundary high 32bit address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_LL_REG          (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x6C)  /* the MCTP cache/snp configuration DAW 1 low boundary low 32bit address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_LH_REG          (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x70)  /* the MCTP cache/snp configuration DAW 1 low boundary high 32bit address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_HL_REG          (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x74)  /* the MCTP cache/snp configuration DAW 1 high boundary low 32bit address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_HH_REG          (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x78)  /* the MCTP cache/snp configuration DAW 1 high boundary high 32bit address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAW_0_H_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x7C)  /* high 16bit of  DAW 0 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAW_0_L_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x80)  /* low 32bit of DAW 0 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAW_1_H_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x84)  /* high 16bit of  DAW 1 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAW_1_L_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x88)  /* low 32bit of  DAW 1 upper address */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_ATTR_1_REG                 (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x8C)  /* the memory attribute control of DMA */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_ATTR_2_REG                 (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x90)  /* the memory attribute control of DMA */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_SDI_IEP_CFG_ATTR_REG           (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x94)  /* the cache/snp attribute control of IEP config reqeust */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_SDI_RCP_ATTR_REG               (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x98)  /* the cache/snp attribute control of RCP transaction */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_SDI_NVME_ATTR_REG              (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x9C)  /* the cache/snp attribute control of NVMe transaction */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_SDI_MCTP_ATTR0_REG             (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0xA0)  /* the cache/snp attribute control of MCTP transaction */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_SDI_MCTP_ATTR1_REG             (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0xA4)  /* the cache/snp attribute control of MCTP transaction */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_SDI_MCTP_ATTR2_REG             (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0xA8)  /* the cache/snp attribute control of MCTP transaction */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_WEIGHT_CFG_REG                      (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0xAC)  /* weight for WRR arbitration */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_ACTIVE_CFG_REG                      (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0xB0)  /* active cfg */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_RCP_DEEP_CFG_REG                    (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0xB4)  /* rcp table depth cfg */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_NVME_DEEP_CFG_REG                   (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0xB8)  /* nvme table depth cfg */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_MODE_CFG_REG                        (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0xBC)  /* rba mode cfg */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_ICG_CFG_REG                         (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0xC0)  /* rab icg cfg */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_ENG_SEC_CTRL_REG                        (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0xC4)  /* the sec ctrl for DMA，INT and NVME */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_DFX_RBA_CNT_HEAD_REG                    (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x800) /* dfx_rba_cnt_head */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_DFX_RBA_CNT_ERR_HEAD_REG                (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x804) /* dfx_rba_cnt_err_head */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_DFX_RBA_BUFFER_USEDDEEP_MCTP_REG        (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x808) /* dfx_rba_buffer_used */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_DFX_RBA_BUFFER_USEDDEEP_OTHER_REG       (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x80C) /* dfx_rba_buffer_used */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_DFX_RBA_ARBITER_EN_REG                  (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x810) /* dfx_rba_arbiter_en */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_DFX_RBA_IDLE_REG                        (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x81C) /* dfx_rba_idle */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_RAM_ECC_ERR_INJ_REG                 (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x820) /* RAM ECC inject control */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_RAM_ECC_ERR_ADDR_RD_REG             (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x824) /* RAM ECC err addr */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_RAM_ECC_1BIT_ERR_CNT_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x828) /* RAM ECC 1bit err cnt */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_RAM_ECC_2BIT_ERR_CNT_REG            (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x82C) /* RAM ECC 2bit err cnt */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_CE_REG                    (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x830) /* rba interrupt read only status for correctable error */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_NFE_REG                   (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x834) /* rba interrupt read only status for non-fatal error */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_FE_REG                    (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x838) /* rba interrupt read only status for fatal error */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_SET_REG                      (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x840) /* rba interrupt set configure */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_MASK_REG                     (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x844) /* rba interrupt mask configure */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_STATUS_REG                   (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x848) /* rba interrupt status */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_REG                       (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x84C) /* rba interrupt read only status */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_RBA_RAM_ECC_ERR_ADDR_WR_REG             (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x850) /* RAM ECC err addr */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_DFX_RBA_PAB_PAGE_FAULT_RSLT_IDX_REG     (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x854) /* RBA lookup result idx when iep page fault */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_DFX_RBA_PAB_PAGE_FAULT_RSLT_PA_LOW_REG  (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x858) /* RBA lookup physical address when iep page fault */
#define HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_DFX_RBA_PAB_PAGE_FAULT_RSLT_PA_HIGH_REG (HiPCIECTRL50V200_HIPCIEC50_AP_ENGINE_REG_BASE + 0x85C) /* RBA lookup physical address when iep page fault */

#endif // __HIPCIEC50_AP_ENGINE_REG_REG_OFFSET_H__
